1. Field of the Invention
The present invention is related to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving image flicker.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, small size and low power consumption, have gradually replaced traditional cathode ray tube (CRT) displays and been widely used in various electronic products, such as notebook computers, personal digital assistants (PDAs), flat panel TVs, or mobile phones.
FIG. 1 is a diagram illustrating a prior art LCD device 100. The LCD device 100 includes a source driver 110, a gate driver 120, a timing controller 130, a plurality of data lines DL1-DLm, a plurality of gate lines GL1-GLn, and a pixel matrix. The pixel matrix includes a plurality of pixel units PX each having a thin film transistor (TFT) switch, a liquid crystal capacitor CLC and a storage capacitor CST, and respectively coupled to a corresponding data line, a corresponding gate line and a common voltage Vcom. The timing controller 130 can generate control signals for operating the source driver 110 and the gate driver 120, such as a start pulse signal VST and clock signals CK, XCK. The source driver 110 can generate data driving signals SD1-SDm corresponding to display images. The gate driver 120 includes a plurality of shift register units SR1-SRn and having output ends OUT1-OUTn coupled to the corresponding gate lines GL1-GLn, respectively. According to the clock signals CK, XCK and the start pulse signal VST, the gate driver 120 sequentially outputs the gate driving signals SG1-SGn for turning on the TFT switches. In order to provide sufficient driving, the shift register units SR1-SRn normally adopt large-size output TFT switches.
FIG. 2 is a diagram of a prior art LCD device 200. The LCD device 200 includes a source driver 210, a gate driver 220, a timing controller 230, a charge-sharing circuit 240, a plurality of data lines DL1-DLm, a plurality of gate lines GL1-GLn, and a pixel matrix. The pixel matrix includes a plurality of pixel units PX each having a TFT switch, a liquid crystal capacitor CLC and a storage capacitor CST, and respectively coupled to a corresponding data line, a corresponding gate line and a common voltage Vcom. The timing controller 230 can generate control signals for operating the source driver 210 and the gate driver 220, such as a start pulse signal VST, clock signals CK, XCK, and an output enable signal OE. The source driver 210 can generate data driving signals SD1-SDm corresponding to display images. The charge-sharing circuit 240 can perform charge-sharing on the clock signals CK and XCK according to the output enable signal OE, thereby generating corresponding clock signals O_CK and O_XCK. The gate driver 220 includes a plurality of shift register units SR1-SRn having output ends OUT1-OUTn respectively coupled to the corresponding gate lines GL1-GLn. According to the clock signals CK, XCK and the start pulse signal VST, the gate driver 220 sequentially outputs the gate driving signals SG1-SGn for turning on the TFT switches. In order to provide sufficient driving, the shift register units SR1-SRn normally adopt large-size output TFT switches, and the values of parasitic capacitance at the output ends OUT1-OUTn are represented by C1-Cn, respectively.
In the prior art LCD devices 100 and 200, the parasitic capacitance of the output ends OUT1-OUTn of the gate driver 120 or 220 may differ, resulting in different amount of RC loading for the gate driving signals SG1-SGn. This kind of gate pulse distortion largely influences the display quality.